A general rule in integrated circuits is that higher operating speeds require more power. Even in CMOS integrated circuits this is true.
CMOS static RAM integrated circuits typically are arranged in a matrix of rows and columns of memory cells. Words lines extend along the rows of memory cells to access a particular row. Pairs of complementary bit lines extend along the columns of memory cells to read (or write) information from (or to) the accessed memory cell selected by one of the word lines.
In the read operation of one type of CMOS static RAM, one of the differential bit lines which connect a column of memory cells is coupled to a current source by the selected memory cell, while the other bit line is not, for high speed operation. Which bit line is coupled to a current source is determined by the information stored in the selected memory cell.
A problem with high speed operation is that the accessed memory cell causes relatively small signals on the bit lines which operate with small currents and have large capacitances. During a read operation the small signals must converted to the full CMOS logic levels as quickly as possible. However, a mere increase in current is constrained in any design of a high-speed sense amplifier sensing the signals on the bit lines because unrestricted power consumption in integrated circuits is undesirable.
The present invention provides for a sense amplifier which can read that type of memory cell at very high speeds, but at relatively low power.